The FPGA-based graphics processor is designed for affordable embedded applications, with the team now exploring an 8–16 core architecture and a possible 65nm ASIC
An e-rickshaw dashboard, a navigation terminal on a small fishing boat or an educational e-book reader may not be the first things that come to mind when talking about graphics processors. But these are among the applications that researchers at IIT Delhi have in mind for an indigenous micro-GPU they have developed.
Researchers in the institute’s Electrical Engineering Department have designed what they describe as the first working, demonstrable indigenously designed micro-GPU from a university in India.
The team says the development could help reduce dependence on imported GPUs and enable indigenous graphics and display-processing systems for affordable embedded applications.
From an idea to a working processor
The project has been led by M.Tech students Nammi Akash and M. Ravi Teja, under the guidance of Prof. Jayadeva and Prof. Kaushik Saha of IIT Delhi’s Electrical Engineering Department.
The researchers have demonstrated programmable graphics rendering using a custom floating-point GPU engine implemented entirely in Register Transfer Language (RTL) and mapped onto a Spartan-7 Field Programmable Gate Array (FPGA) platform.
The distinction is important for the project: the team has not merely proposed a GPU architecture but has demonstrated the graphics processor working on an FPGA platform.
The hardware architecture has been designed as a scalable programmable graphics processor IP, which IIT Delhi says could be used for applications where affordable graphics and display capabilities are required.
These include industrial control displays, low-cost human-machine interfaces, e-rickshaw dashboard navigators, inland-water navigation terminals for small fishing boats and educational e-book readers.
The architecture can potentially be mapped onto silicon through an Application-Specific Integrated Circuit (ASIC) or implemented on programmable hardware such as FPGAs.
The students behind the project
For Akash and Ravi Teja, the objective was to develop a compact but genuinely programmable graphics-processing architecture that could first be implemented on an FPGA and eventually realised as an ASIC.
In a joint statement, the students said they hoped that indigenous hardware systems could support affordable digital-access platforms and contribute towards bridging the digital divide.
The project also brought together several areas of engineering, including arithmetic hardware, programmable processor architecture, compilers and embedded systems.
Prof. Jayadeva said the work demonstrates the educational and research potential of indigenous programmable graphics hardware for affordable and socially useful computing platforms. He noted that several innovations were required to realise the design on a standard FPGA board.
Prof. Kaushik Saha said the project encourages students to integrate arithmetic hardware, programmable architectures, compilers and embedded-systems thinking within a unified framework while addressing wider accessibility challenges.
What comes next
The current micro-GPU is only the first stage of the team’s roadmap.
The researchers are exploring an 8–16 core vector-style graphics processor architecture, along with an optimised compiler and graphics software toolchain.
They are also looking towards a proof of concept at a 65nm ASIC process node. According to the researchers, mature semiconductor process nodes such as 65nm could potentially enable economically viable and practically useful indigenous graphics silicon for embedded-system applications.
That stage has not yet been achieved. The team says it plans to seek funding for ASIC development, system integration and eventual commercialisation.
For now, IIT Delhi’s achievement is a working demonstration of an indigenous programmable micro-GPU on an FPGA. The next challenge for the researchers is to take that demonstration towards a larger multi-core architecture and, eventually, silicon.
